Lattice Mapping Report File for Design Module 'BCDHEX' Design Information Command line: map -a MachXO3L -p LCMXO3L-6900C -t CABGA256 -s 5 -oc Commercial BCDHEX_impl1.ngd -o BCDHEX_impl1_map.ncd -pr BCDHEX_impl1.prf -mp BCDHEX_impl1.mrp -lpf D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/impl1/BCDHEX_impl1.lpf -lpf D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/BCDHEX.lpf -c 0 -gui -msgset D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/promote.xml Target Vendor: LATTICE Target Device: LCMXO3L-6900CCABGA256 Target Performance: 5 Mapper: xo3c00a, version: Diamond (64-bit) 3.12.0.240.2 Mapped on: 04/14/22 10:38:46 Design Summary Number of registers: 0 out of 7485 (0%) PFU registers: 0 out of 6864 (0%) PIO registers: 0 out of 621 (0%) Number of SLICEs: 4 out of 3432 (0%) SLICEs as Logic/ROM: 4 out of 3432 (0%) SLICEs as RAM: 0 out of 2574 (0%) SLICEs as Carry: 0 out of 3432 (0%) Number of LUT4s: 7 out of 6864 (0%) Number used as logic LUTs: 7 Number used as distributed RAM: 0 Number used as ripple logic: 0 Number used as shift registers: 0 Number of PIO sites used: 11 + 4(JTAG) out of 207 (7%) Number of block RAMs: 0 out of 26 (0%) Number of GSRs: 0 out of 1 (0%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 2 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 0 Number of Clock Enables: 0 Number of LSRs: 0 Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net X_c_0: 7 loads Net X_c_1: 7 loads Net X_c_2: 7 loads Net X_c_3: 7 loads Net Y_c_0: 1 loads Net Y_c_1: 1 loads Net Y_c_2: 1 loads Net Y_c_3: 1 loads Net Y_c_4: 1 loads Net Y_c_6: 1 loads Number of warnings: 0 Number of errors: 0 Design Errors/Warnings No errors or warnings present. IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | X[0] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | X[1] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | X[2] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | X[3] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | Y[6] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | Y[5] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | Y[4] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | Y[3] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | Y[2] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | Y[1] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | Y[0] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ Removed logic Block i2 undriven or does not drive anything - clipped. Block GSR_INST undriven or does not drive anything - clipped. Block i117 undriven or does not drive anything - clipped. Signal VCC_net undriven or does not drive anything - clipped. Signal GND_net undriven or does not drive anything - clipped. Run Time and Memory Usage ------------------------- Total CPU Time: 4 secs Total REAL Time: 5 secs Peak Memory Usage: 55 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.