Setting log file to 'D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/standard.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/standard.vhd(9,9-9,17) (VHDL-1014) analyzing package 'standard'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/std_1164.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package 'std_logic_1164'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body 'std_logic_1164'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/mgc_qsim.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package 'qsim_logic'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body 'qsim_logic'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/numeric_bit.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package 'numeric_bit'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body 'numeric_bit'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/numeric_std.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package 'numeric_std'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body 'numeric_std'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/textio.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package 'textio'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body 'textio'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/std_logic_textio.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package 'std_logic_textio'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body 'std_logic_textio'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_attr.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package 'attributes'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_misc.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package 'std_logic_misc'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body 'std_logic_misc'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/math_real.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/math_real.vhd(56,9-56,18) (VHDL-1014) analyzing package 'math_real'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/math_real.vhd(685,14-685,23) (VHDL-1013) analyzing package body 'math_real'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/mixed_lang_vltype.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package 'vl_types'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body 'vl_types'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_arit.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package 'std_logic_arith'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body 'std_logic_arith'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_sign.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package 'std_logic_signed'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body 'std_logic_signed'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_unsi.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package 'std_logic_unsigned'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body 'std_logic_unsigned'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/synattr.vhd'
INFO - C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package 'attributes'
(VERI-1482) Analyzing Verilog file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo3l.v'
(VHDL-1481) Analyzing VHDL file 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo3l.vhd'
(VHDL-1481) Analyzing VHDL file 'D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/BCDHEX.vhd'
INFO - D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/BCDHEX.vhd(6,8-6,14) (VHDL-1012) analyzing entity 'bcdhex'
INFO - D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/BCDHEX.vhd(11,14-11,23) (VHDL-1010) analyzing architecture 'verhalten'
INFO - D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/BCDHEX.vhd(6,8-6,14) (VHDL-1067) elaborating 'BCDHEX(VERHALTEN)'
WARNING - D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/BCDHEX.vhd(13,7-13,8) (VHDL-1037) selected assignment statement does not cover all choices. 'others' clause is needed
Done: design load finished with (0) errors, and (1) warnings