Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.12.0.240.2

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Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Thu Apr 14 10:38:40 2022


Command Line:  synthesis -f BCDHEX_impl1_lattice.synproj -gui -msgset D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/promote.xml 

Synthesis options:
The -a option is MachXO3L.
The -s option is 5.
The -t option is CABGA256.
The -d option is LCMXO3L-6900C.
Using package CABGA256.
Using performance grade 5.
                                                          

##########################################################

### Lattice Family : MachXO3L

### Device  : LCMXO3L-6900C

### Package : CABGA256

### Speed   : 5

##########################################################

                                                          

INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = BCDHEX.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/xo3c00a/data (searchpath added)
-p D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/impl1 (searchpath added)
-p D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment (searchpath added)
VHDL library = work
VHDL design file = D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/BCDHEX.vhd
NGD file = BCDHEX_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo3l.v. VERI-1482
Compile design.
Compile Design Begin
INFO - synthesis: The default VHDL library search path is now "D:/Stefan Bischoff/Zittau/Vorlesungen/Vorlesung Digitaltechnik/Bischoff Software/HDL/FPGA MACHX03/BCD-7 Segment/impl1". VHDL-1504
Analyzing VHDL file d:/stefan bischoff/zittau/vorlesungen/vorlesung digitaltechnik/bischoff software/hdl/fpga machx03/bcd-7 segment/bcdhex.vhd. VHDL-1481
INFO - synthesis: d:/stefan bischoff/zittau/vorlesungen/vorlesung digitaltechnik/bischoff software/hdl/fpga machx03/bcd-7 segment/bcdhex.vhd(6): analyzing entity bcdhex. VHDL-1012
INFO - synthesis: d:/stefan bischoff/zittau/vorlesungen/vorlesung digitaltechnik/bischoff software/hdl/fpga machx03/bcd-7 segment/bcdhex.vhd(11): analyzing architecture verhalten. VHDL-1010
unit BCDHEX is not yet analyzed. VHDL-1485
unit BCDHEX is not yet analyzed. VHDL-1485
d:/stefan bischoff/zittau/vorlesungen/vorlesung digitaltechnik/bischoff software/hdl/fpga machx03/bcd-7 segment/bcdhex.vhd(6): executing BCDHEX(VERHALTEN)

WARNING - synthesis: d:/stefan bischoff/zittau/vorlesungen/vorlesung digitaltechnik/bischoff software/hdl/fpga machx03/bcd-7 segment/bcdhex.vhd(9): replacing existing netlist BCDHEX(VERHALTEN). VHDL-1205
Top module name (VHDL): BCDHEX
Loading NGL library 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo3c6900.nph' in environment: C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.16.
Top-level module name = BCDHEX.



GSR will not be inferred because no asynchronous signal was found in the netlist.
Applying 200.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in BCDHEX_drc.log.
Loading NGL library 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/Program Files (x86)/LatticeDiamond/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
WARNING - synthesis: logical net 'GND_net' has no load.
WARNING - synthesis: DRC complete with 1 warnings.
All blocks are expanded and NGD expansion is successful.
Writing NGD file BCDHEX_impl1.ngd.

################### Begin Area Report (BCDHEX)######################
Number of register bits => 0 of 7485 (0 % )
GSR => 1
IB => 4
LUT4 => 7
OB => 7
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 0
Clock Enable Nets
Number of Clock Enables: 0
Top 0 highest fanout Clock Enables:
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : X_c_3, loads : 7
  Net : X_c_2, loads : 7
  Net : X_c_1, loads : 7
  Net : X_c_0, loads : 7
  Net : Y_c_0, loads : 1
  Net : Y_c_1, loads : 1
  Net : Y_c_2, loads : 1
  Net : Y_c_3, loads : 1
  Net : Y_c_4, loads : 1
  Net : Y_c_5, loads : 1
################### End Clock Report ##################

Peak Memory Usage: 71.500  MB

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Elapsed CPU time for LSE flow : 3.094  secs
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